ORIGINAL FPGA
; SC1 memory writes
Sample db addr irq halt avma Comments Sample db addr irq halt avma
18953 86 F285 0 1 1 ; LDA #0x02 | 18953 86 F285 0 1 1
18954 02 F286 0 1 1 | 18954 02 F286 0 1 1
18955 B7 F287 0 1 1 ; STA 0xCA00 | 18955 B7 F287 0 1 1
18956 CA F288 0 1 1 | 18956 CA F288 0 1 1
18957 00 F289 0 1 0 | 18957 00 F289 0 1 0
18958 C6 FFFF 0 1 1 | 18958 00 FFFF 0 1 1
18959 02 CA00 0 0 1 ; *fast SC1 memory copy | 18959 02 CA00 0 0 1
; HALT goes active for
; SC1 operation
...
19241 86 F296 0 1 1 ; LDA #0x060 | 19241 86 F296 0 1 1
19242 06 F297 0 1 1 | 19242 06 F297 0 1 1
19243 B7 F298 0 1 1 ; STA 0xCA00 | 19243 B7 F298 0 1 1
19244 CA F299 0 1 1 | 19244 CA F299 0 1 1
19245 00 F29A 0 1 0 | 19245 00 F29A 0 1 0
19246 C6 FFFF 0 1 1 | 19246 00 FFFF 0 1 1
19247 06 CA00 0 0 1 ; *slow SC1 memory copy | 19247 06 CA00 0 0 1
; Interrupt request and execute IRQ service routine
23000 3E CB00 1 1 1 | 23000 3E CB00 1 1 1
23001 25 F2BE 1 1 1 | 23001 25 F2BE 1 1 1
23002 FB F2BF 1 1 0 | 23002 FB F2BF 1 1 0
23003 FF FFFF 1 1 1 | 23003 00 FFFF 1 1 1
23004 3A F2BB 1 1 1 | 23004 3A F2BB 1 1 1
23005 91 F2BC 0 1 0 ; IRQ active | 23005 91 F2BC 0 1 0
23006 D7 FFFF 0 1 1 | 23006 00 FFFF 0 1 1
23007 91 F2BC 0 1 1 | 23007 91 F2BC 0 1 1
23008 91 F2BC 0 1 0 | 23008 91 F2BC 0 1 0
23009 D7 FFFF 0 1 1 | 23009 00 FFFF 0 1 1
23010 BC BFFB 0 1 1 ; stack operations | 23010 BC BFFB 0 1 1
23011 F2 BFFA 0 1 1 | 23011 F2 BFFA 0 1 1
23012 00 BFF9 0 1 1 | 23012 00 BFF9 0 1 1
23013 00 BFF8 0 1 1 | 23013 00 BFF8 0 1 1
23014 FE BFF7 0 1 1 | 23014 FE BFF7 0 1 1
23015 9A BFF6 0 1 1 | 23015 9A BFF6 0 1 1
23016 0D BFF5 0 1 1 | 23016 0D BFF5 0 1 1
23017 01 BFF4 0 1 1 | 23017 01 BFF4 0 1 1
23018 CB BFF3 0 1 1 | 23018 CB BFF3 0 1 1
23019 01 BFF2 0 1 1 | 23019 01 BFF2 0 1 1
23020 03 BFF1 0 1 1 | 23020 03 BFF1 0 1 1
23021 89 BFF0 0 1 0 | 23021 89 BFF0 0 1 0
23022 CF FFFF 0 1 1 | 23022 00 FFFF 0 1 1
23023 F2 FFF8 0 1 1 ; CPU reads | 23023 F2 FFF8 0 1 1
23024 C5 FFF9 0 1 0 ; IRQ vector | 23024 C5 FFF9 0 1 0
23025 C7 FFFF 0 1 1 | 23025 00 FFFF 0 1 1
23026 34 F2C5 0 1 1 ; CPU IRQ routine | 23026 34 F2C5 0 1 1
23027 37 F2C6 0 1 0 ; execute | 23027 37 F2C6 0 1 0
; end of the capture samples
; original and FPGA board code executon remains in
; sync after 1 million cycles
1048554 FC F1FC 0 1 1 | 1048554 FC F1FC 0 1 1
1048555 A0 F1FD 0 1 1 | 1048555 A0 F1FD 0 1 1
1048556 15 F1FE 0 1 0 | 1048556 15 F1FE 0 1 0
1048557 D7 FFFF 0 1 1 | 1048557 00 FFFF 0 1 1
1048558 00 A015 0 1 1 | 1048558 7A A015 0 1 1
1048559 38 A016 0 1 1 | 1048559 64 A016 0 1 1
1048560 E3 F1FF 0 1 1 | 1048560 E3 F1FF 0 1 1
1048561 81 F200 0 1 1 | 1048561 81 F200 0 1 1
1048562 FD F201 0 1 0 | 1048562 FD F201 0 1 0
1048563 FF FFFF 0 1 0 | 1048563 00 FFFF 0 1 0
1048564 FF FFFF 0 1 0 | 1048564 00 FFFF 0 1 0
1048565 FF FFFF 0 1 1 | 1048565 00 FFFF 0 1 1
1048566 00 B9AC 0 1 1 | 1048566 00 B9AC 0 1 1
1048567 00 B9AD 0 1 0 | 1048567 00 B9AD 0 1 0
1048568 C6 FFFF 0 1 1 | 1048568 00 FFFF 0 1 1
1048569 FD F201 0 1 1 | 1048569 FD F201 0 1 1
1048570 A0 F202 0 1 1 | 1048570 A0 F202 0 1 1
1048571 15 F203 0 1 0 | 1048571 15 F203 0 1 0